Technology

Fab vs OSAT vs chip design: the chip value chain, explained

A chip passes through three very different businesses before it reaches a phone or a car: design, wafer fabrication and packaging. Here is who does what, where the money sits, and which of India's 12 approved plants belongs to which stage.

Chander Prakash

By Founder & Editor

9 min read

Illustrative cover: Fab vs OSAT vs chip design: the chip value chain, explained
Illustration: Pointales

Three different kinds of company make a chip. One designs it, using software and licensed building blocks. One fabricates it, printing billions of transistors onto silicon wafers in a plant that costs billions of dollars. One cuts the wafer into chips, seals each in a protective package and tests it. Very few companies do all three. As of October 2026, India has five plants in commercial production, and every one of them is in the third group. Knowing which stage a plant belongs to is the quickest way to judge what an announcement actually means.

What the stages are

The industry calls the first two stages the front end and the third the back end. A fourth step, selling the finished chip to a device maker, is distribution.

StageWhat it doesWho does it globallyIndia examples
Design, EDA and IPEngineers specify and verify the circuit using electronic design automation (EDA) software, often licensing ready-made blocks such as a processor coreNvidia, Qualcomm, AMD, MediaTek (design); Synopsys, Cadence (EDA); Arm (IP)Design centres of global firms; 104 start-ups and 315 institutions under the government’s design scheme
Wafer fabrication (“fab”)Prints the circuit onto silicon wafers in hundreds of steps inside a clean roomTSMC, Samsung, Intel, GlobalFoundries, UMC, SMIC; memory makers such as Micron and SK hynixTata Electronics with PSMC, Dholera (under construction)
Assembly, test and packaging (OSAT / ATMP)Cuts the wafer into individual chips (“dies”), wires and seals each into a package, and tests itASE (Taiwan), Amkor (US), JCET (China); the fabs’ own back-end plantsMicron Sanand, Kaynes Sanand, CG Semi Sanand, CDIL Mohali, Suchi Surat (all in production); Tata Assam (pilot)
Into devicesFinished chips go to phone, car, server and appliance makersFoxconn, Dell, carmakersDell’s India laptops take Micron’s Sanand memory

Two acronyms cover the back end. OSAT means outsourced semiconductor assembly and test, a company that packages chips for others. ATMP (assembly, test, marking and packaging) is the activity itself; the Indian government uses it for any back-end plant, including ones a chipmaker runs for itself. Our pillar on India’s semiconductor push lists every approved project and its timeline; this article is about what kind of plant each one is.

Design is where the chip’s function is decided. With billions of transistors on a chip, nobody draws circuits by hand: EDA software from Synopsys or Cadence lays out and verifies the design, and designers license ready-made blocks, such as an Arm processor core, paying a fee per chip shipped.

Where the money sits

The stages differ enormously in what they cost and what they earn. The OECD, drawing on a 2021 study by the Semiconductor Industry Association and BCG, puts it this way: design represents about half of the industry’s value added but only 10–15% of physical capital expenditure; wafer fabrication about a quarter of value added but almost two-thirds of capex; and assembly, test and packaging only about 5% of value added but 10–15% of capex. The underlying BCG/SIA study uses 2019 data, so treat the shares as a shape rather than today’s exact split.

That shape explains the industry’s money. Global chip sales reached $791.7 billion in 2025, up 25.6%, according to the SIA. TSMC alone, which only fabricates, reported 2025 revenue of $122.42 billion, with 74% of wafer revenue from its 7nm-and-below processes. The specialist packagers are far smaller: Amkor, the largest US-based OSAT, reported $6.71 billion in 2025 sales.

India’s project list shows the same gap in capital. The Cabinet’s February 2024 approval priced Tata’s Dholera fab at ₹91,000 crore for 50,000 wafer starts a month. Kaynes Semicon’s Sanand back-end plant, approved in September 2024, cost ₹3,300 crore for 60 lakh (6 million) chips a day. One fab costs about as much as 27 such packaging plants.

Fabless, IDM, foundry, OSAT: four ways to be a chip company

The stages map onto four business models.

  • Fabless companies design chips and own the product, but pay others to make them. Nvidia’s annual report describes “a fabless and contracting manufacturing strategy”: foundries such as TSMC and Samsung “produce our semiconductor wafers”, and contractors handle assembly, testing and packaging. Qualcomm, AMD and MediaTek work the same way.
  • Foundries fabricate wafers for fabless customers and sell nothing under their own name. TSMC’s annual report calls it a “pure-play foundry” that does not design, manufacture or market products under its own brand, so it never competes with its customers. It served 534 customers and made 12,682 different products in 2025.
  • Integrated device manufacturers (IDMs) design and fabricate their own chips. Intel, Samsung’s memory business, Texas Instruments and Micron are IDMs. Micron’s new Sanand plant takes DRAM and NAND wafers “from Micron’s global manufacturing network” and turns them into finished memory products; the wafers are made in Micron’s own fabs abroad.
  • OSATs do the back end for anyone; ASE, Amkor and JCET are the largest specialists. In India, CG Semi, Kaynes, Suchi and Tata’s Assam plant are OSATs, while Micron’s Sanand unit is an IDM’s captive back end.

The models blur: Intel is an IDM that also offers foundry services, and Samsung is an IDM in memory and a foundry in logic. The one constant is that a fab, whoever owns it, is the scarce and expensive asset, which is why the nodes it can run matter so much (our explainer on what “3nm” and “2nm” really mean covers that).

Why packaging matters more than it used to

For decades the back end was the cheap, labour-heavy end of the chain, and the 5% value-added figure reflects that. Two changes are pushing it up the value ladder.

The first is chiplets. Instead of one giant chip, designers build several smaller dies and join them inside one package. Nvidia’s Blackwell AI processor, announced in March 2024, has 208 billion transistors across “two-reticle limit GPU dies connected by 10 TB/second chip-to-chip link” into what behaves as one chip. The “reticle limit” is the largest area a lithography machine can print in one exposure; splitting the chip is the only way past it, and joining the dies is a packaging job.

The second is memory stacking. AI accelerators sit beside stacks of high-bandwidth memory, placed on a silicon base that carries thousands of connections. Nvidia says it uses TSMC’s CoWoS process for this packaging, and TSMC’s annual report lists CoWoS, InFO and SoIC among the technologies it is scaling. Why AI needs so many of these chips is explained in our piece on what GPUs are.

Because chiplets from different companies need to talk to each other, the industry set a standard. The UCIe consortium, formed in March 2022 by ASE, AMD, Arm, Google Cloud, Intel, Meta, Microsoft, Qualcomm, Samsung and TSMC, with Nvidia and Alibaba joining the board that August, exists to foster “a universal interconnect at the package-level”. That an OSAT, ASE, sits among the founders alongside the biggest designers and foundries says how far packaging has moved. The Indian government has noticed: “Advanced Packaging” is one of the six pillars of Semicon 2.0, the ₹1,27,500 crore second phase approved in July 2026, according to the India Semiconductor Mission.

Where India sits in the chain

Design is India’s established strength. The government’s investment agency says Indian engineers account for “around 20% of the world’s semiconductor design workforce”. The figure is widely repeated, but no public dataset is cited for it, and Carnegie India’s review of the mission adds the caveat that this workforce “often follows specifications prescribed by global multinational firms” and that owning the underlying intellectual property in India “remains elusive”. The government’s own count, given at SEMICON India in September 2026, is 70,000 design engineers trained and EDA tools deployed across more than 500 organisations under the first phase of the mission.

Manufacturing is where the 12 approved projects (about ₹1.64 lakh crore, per the May 2026 Cabinet release) sit. Sorted by stage, as of October 2026:

  1. Silicon wafer fab (one): Tata Electronics with Taiwan’s PSMC at Dholera, Gujarat. Approved for 50,000 wafer starts a month, with the Cabinet release naming 28nm compute chips and power-management chips. Bloomberg reported in July 2026 that output will begin on 90nm; Tata told Outlook Business it always planned to start with 55nm and 90nm, “followed by 28nm”, and the minister now expects commercial production by mid-2028.
  2. Compound semiconductor fabs (two): SiCSem’s silicon carbide plant in Odisha, 60,000 wafers a year plus packaging for 96 million units, and Crystal Matrix’s gallium nitride display fab with ATMP at Dholera, approved in May 2026. These print on different materials, for power electronics and micro-LED displays, and are far smaller than a silicon logic fab.
  3. Back-end plants (the rest): Micron Sanand (memory, producing since February 2026), Kaynes Sanand (producing since March), CG Semi Sanand (inaugurated 4 July 2026 at 20 crore units a year), CDIL Mohali and Suchi Surat (both switched on at SEMICON India on 17 September 2026, making “five operational commercial semiconductor ATMP units”), Tata’s Assam OSAT (pilot output reported in early October, with a capacity of up to 48 million chips a day when ramped), ASIP in Andhra Pradesh, and 3D Glass Solutions’ glass-substrate packaging unit in Odisha. HCL-Foxconn’s Jewar unit, described by PIB as taking 20,000 wafers a month and producing 36 million display driver chips, is also a wafers-in, chips-out plant.

The pattern: five plants running, all back end; one silicon fab not expected before 2028; and a large design workforce that mostly works on others’ chips.

How to read “India’s first chip” headlines

Every operating Indian plant today starts from a wafer fabricated elsewhere. Micron’s Sanand unit, the largest of them, is explicit that its wafers come from its global network. That is not a criticism: packaging and testing is real manufacturing, the fastest stage to build, and the one whose importance is rising. But it is a different claim from “India now makes chips”.

Three questions settle what any announcement means:

  1. Where was the wafer made? If the answer is Taiwan, Japan, Singapore or the United States, the Indian plant is doing the back end. Until Dholera runs, that is every plant.
  2. Who designed the chip, and who owns the design? A chip packaged in Sanand for Renesas or assembled for Micron is their product. Indian ownership of the design is a separate, slower goal that Semicon 2.0’s design pillar targets.
  3. What node and what material? 28nm silicon is a mature logic node suited to cars, power and industrial chips; silicon carbide and gallium nitride are power and display technologies. None of the approved projects is a leading-edge logic fab, and the pillar explains why that is a sensible starting point.

The point: Chip design earns about half the industry’s value with little capital; fabs earn a quarter but need two-thirds of the capital; packaging has been the cheap end but is becoming strategic as chips are built from chiplets. India is strong in design-for-others, has five back-end plants running, and will not fabricate silicon at commercial scale until Dholera starts around 2028. Read every “made in India chip” headline by asking which of the three stages happened here.

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Chander Prakash

Chander Prakash Founder & Editor

Chander Prakash is the founder and editor of Pointales. He reviews every story before it is published and sets the publication's editorial standards, with a focus on clear, well-sourced explanations of business and technology.

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