Technology

What “3nm” and “2nm” really mean in chips

Chip names like 3nm and 2nm sound like measurements, but they stopped describing any physical size decades ago. Here is what the numbers actually signal, what improves at each step, and why India's first fab is aiming at 28nm.

Chander Prakash

By Founder & Editor

7 min read

Illustrative cover: What "3nm" and "2nm" really mean in chips
Illustration: Pointales

“3nm” and “2nm” are names for generations of chip-manufacturing technology, not measurements. Until the mid-1990s, the number roughly matched the length of a transistor’s gate, the smallest feature on the chip. Since then the two have drifted apart, and today no part of a “2nm” chip is 2 nanometres wide. A smaller number still means a newer, generally denser and more power-efficient process within one company’s line-up, but it says little when you compare one company’s chip with another’s.

What the number used to measure

A transistor is a tiny switch. Current flows through a channel, and a “gate” above it turns that current on or off. For decades, chipmakers named each new manufacturing generation, or node, after the gate length or the finest line they could print.

IEEE Spectrum, the magazine of the engineering body IEEE, notes that in the mid-1990s the 0.35-micron (350nm) node accurately described the finest features on a chip. Then the link broke. Transistors made on the so-called 130nm node actually had 70nm gates, and “most of the critical features of a 7-nm transistor are actually considerably larger than 7 nm,” the magazine reported in 2020.

Paolo Gargini, who leads the IEEE International Roadmap for Devices and Systems (IRDS), the industry’s main technology roadmap, told Spectrum that the node number had “absolutely no meaning, because it had nothing to do with any dimension that you can find on the die.”

What the real dimensions look like

The IRDS describes chips by measured pitches instead of a single number. Its notation G48M36T1, for example, means a contacted gate pitch (the spacing from one transistor gate to the next) of 48nm, a tightest metal-wiring pitch of 36nm and one tier of devices. Spectrum reported that this was the IRDS figure for the then-upcoming “5nm” chips.

In other words, a “5nm” chip has gates spaced about ten times further apart than its name implies. The IRDS 2023 roadmap also projects that the physical channel length will stop shrinking at around 12nm, and states plainly that “there is not yet a consensus on the node naming across different foundries and integrated device manufacturers.”

What actually improves at each node

If the name is not a size, what are buyers paying for? Chipmakers describe each node by three gains, usually against their own previous node:

  • Density: more transistors in the same area, so more cores, cache or AI units per chip.
  • Power: the same work using less electricity, which means longer battery life and cooler data centres.
  • Performance: faster switching at the same power.

The companies’ own claims show the pattern. These are marketing figures measured against each firm’s earlier process, so they cannot be compared across companies:

  • TSMC N3 (volume production December 2022): up to 1.6 times the logic density and 30–35% lower power at the same speed compared with its 5nm process, TSMC said.
  • TSMC N2: 10–15% more speed at the same power, or 25–30% less power at the same speed, compared with N3, according to TSMC in 2022.
  • Samsung 3nm (production from June 2022): up to 45% lower power, 23% higher performance and 16% smaller area than its 5nm process for the first generation, Samsung said.
  • Intel 18A: up to 15% better performance per watt and 30% better chip density than Intel 3, Intel said in October 2025.

Why the transistor’s shape changed

Shrinking alone stopped being enough, so the transistor itself has been redesigned twice.

  1. Planar: a flat channel with the gate on top. Used for decades until leakage became a serious problem at small sizes.
  2. FinFET: the channel stands up like a fin and the gate wraps around three sides, giving better control. Intel says it pioneered FinFETs in 2011; TSMC calls its N3 the industry’s most advanced FinFET technology.
  3. Gate-all-around (GAA), or nanosheet: the channel is a stack of thin horizontal sheets, with the gate surrounding each one on all four sides. Samsung was first into production with its version at 3nm; TSMC’s N2 is its first nanosheet node; Intel calls its version RibbonFET.

A second change is backside power delivery. Normally the wires that carry power and the wires that carry signals are crammed together on top of the transistors. Moving power to the underside of the wafer frees space for signals. Intel’s version, PowerVia, debuts in 18A; TSMC calls its version Super Power Rail and announced it for its A16 process, planned for production in 2026.

Why names don’t compare across companies

Because the numbers are labels, each company can set its own. Intel showed this most openly. In July 2021 it renamed its “10nm Enhanced SuperFin” process as Intel 7, and its planned “7nm” as Intel 4, saying the industry’s naming schemes “no longer refer to any specific measurement”. Its fact sheet adds that Intel’s node numbers “do not represent the actual dimension of any physical feature on a transistor.” The rename lined Intel’s names up with rivals’ processes of similar density.

The same logic explains “18A” and “A16”: A stands for angstrom, a tenth of a nanometre, so 18A suggests “1.8nm”. It is still a label.

Who can make leading-edge chips

In practice, three companies make logic chips at the 3nm and 2nm class: TSMC, Samsung and Intel. All three depend on one supplier for the key machine. Printing the finest layers requires extreme ultraviolet (EUV) lithography, which uses light with a 13.5nm wavelength, against 193nm for older deep-ultraviolet tools. ASML, a Dutch company, describes EUV as a technology “entirely unique to ASML”.

NodeCompanyTransistor typeStatus (October 2026)
N3 familyTSMCFinFETIn volume production since December 2022
3nmSamsungGAA (MBCFET)In production since June 2022
N2TSMCGAA (nanosheet)In volume production since Q4 2025
N2PTSMCGAA (nanosheet)Volume production scheduled for second half of 2026
2nm (SF2)SamsungGAAIn mass production; first product Exynos 2600
18AIntelGAA (RibbonFET) + backside power (PowerVia)In production at Fab 52, Arizona; first laptops on sale from 27 January 2026
A16TSMCGAA + backside power (Super Power Rail)Announced for production in 2026

Sources: TSMC 2nm page; TSMC, Dec 2022; Samsung, Jun 2022; Samsung Exynos 2600 page and DigiTimes, Dec 2025; Intel releases of October 2025 and January 2026; TSMC, 24 Apr 2024.

These nodes go into flagship phone processors, PC chips and the accelerators that train and run AI models. The demand behind that last category is explained in our guide to how large language models work.

What this means for India

India’s first commercial silicon fab, Tata Electronics’ plant at Dholera, Gujarat, built with Taiwan’s Powerchip Semiconductor Manufacturing Corp (PSMC), is not chasing 3nm or 2nm. The Cabinet approval of February 2024 lists high-performance compute chips with 28nm technology and power-management chips for electric vehicles, telecom, defence, automotive and consumer electronics, at 50,000 wafer starts a month. Tata said the partnership gives access to 28nm, 40nm, 55nm, 90nm and 110nm processes.

That is a sensible place to start. Most chips in a car, a smart meter, a charger or an industrial motor do not need the densest transistors; they need reliability, high voltages and low cost, which mature nodes deliver with tools that do not require EUV. Our explainer on India’s semiconductor push covers the Dholera timeline and the other approved plants. The same pillar notes that government ambitions for 3nm and 2nm are long-range targets without approved projects behind them yet.

The point: “3nm” and “2nm” are brand names for manufacturing generations, not sizes; the real gate spacing is tens of nanometres. Within one company, a smaller number generally means more transistors, less power or more speed, but comparing numbers across TSMC, Samsung and Intel tells you little. India’s 28nm-and-above fab is not behind the times so much as aimed at the chips most of the economy actually uses.

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Chander Prakash

Chander Prakash Founder & Editor

Chander Prakash is the founder and editor of Pointales. He reviews every story before it is published and sets the publication's editorial standards, with a focus on clear, well-sourced explanations of business and technology.

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